Vector processor classification

According to from where the operands are retrieved in a vector processor, pipe lined vector computers are classified into two architectural configurations:

1. Memory to memory architecture –
   In memory to memory architecture, source operands, intermediate and final results are retrieved (read) directly from the main memory. For memory to memory vector instructions, the information of the base address, the offset, the increment, and the vector length must be specified in order to enable streams of data transfers between the main memory and pipelines. The processors like TI-ASC, CDC STAR-100, and Cyber-205 have vector instructions in memory to memory formats. The main points about memory to memory architecture are:
   • There is no limitation of size
   • Speed is comparatively slow in this architecture
2. Register to register architecture –
   In register to register architecture, operands and results are retrieved indirectly from the main memory through the use of large number of vector registers or scalar registers. The processors like Cray-1 and the Fujitsu VP-200 use vector instructions in register to register formats. The main points about register to register architecture are:
   • Register to register architecture has limited size.
   • Speed is very high as compared to the memory to memory architecture.
   • The hardware cost is high in this architecture.

A block diagram of a modern multiple pipeline vector computer is shown below:

A typical pipe lined vector processor.

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