Various Instructions for five stage Pipeline

Let us consider following decomposition of instruction execution into five stages. These are give as follows below.

1. Fetch Instruction (IF) :
   It reads the next expected instruction into the buffer.

   IR → Mem [PC] ;
   PC → PC + 4 ; 

2. Instruction Decoding (ID) :
   In this, there are following steps:
   • Instruction Decoding, in which determines opcode and operand specifiers.
   • Calculate Operand, in which calculates effective address of each source operand.
   • Fetch Operands, in which fetch each operand from memory.

   A → Regs [IR6,  10] ;
   B → Regs [IR11, ...,  15] ;
   Immediate → (IR16)16## (IR16, ..., 31) 

3. Execute Instruction (EX) :
   It performs indicated operation.

   Memory ref:   ALUoutput  →  A + Immediate ;
   Reg-Reg ALU:  ALU  →  A func B ;
   Reg-Imm ALU:  ALUoutput  →  A op Immediate ;
   Branch:       ALUoutput  →  PC + Immediate;  Cond * (A op 0) 

4. Memory access/branch completion cycle (MEM) :
   It accesses memory.

   Memory ref:  LMD  →  Mem [ALUoutput]  or Mem (ALUoutput)  →  B
   Branch:      if (cond) PC  →  ALUoutput 

5. Write Operand (WO) :
   It stores the result.

   Reg-Reg ALU:   Regs [R16, ...., 20]  →  ALUoutput ;
   Reg-Imm ALU:   Regs [R11, ..., 15] → ALUoutput ;
   Reg-Reg ALU:   Regs [R11, ...., 15]  →  LMD ; 

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