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Tag Archives: GATE-GATE-CS-2005

Let E1 and E2 be two entities in an E/R diagram with simple single-valued attributes. R1 and R2 are two relationships between E1 and E2,… Read More
Suppose the round trip propagation delay for a 10 Mbps Ethernet having 48-bit jamming signal is 46.4 ms. The minimum frame size is (A) 94… Read More
In a packet switching network, packets are routed from source to destination along a single path having two intermediate nodes. If the message size is… Read More
Consider the following code fragment: if (fork() == 0) { a = a + 5; printf(“%d,%d\n”, a, &a); } else { a = a –5;… Read More
Suppose n processes, P1, …. Pn share m identical resource units, which can be reserved and released one at a time. The maximum resource requirement… Read More
Consider a disk drive with the following specifications: 16 surfaces, 512 tracks/surface, 512 sectors/track, 1 KB/sector, rotation speed 3000 rpm. The disk is operated in… Read More
A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 microsec. The… Read More
A 5 stage pipelined CPU has the following sequence of stages: IF — Instruction fetch from instruction memory, RD — Instruction decode and register read,… Read More
Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit addresses. The number of bits needed… Read More
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the… Read More
Consider a three word machine instruction ADD A[R0], @ B The first operand (destination) “A [R0]” uses indexed addressing mode with R0 as the index… Read More
Consider the following circuit. The flip-flops are positive edge triggered D FFs. Each state is designated as a two bit string Q0Q1. Let the initial… Read More
The following diagram represents a finite state machine which takes as input a binary number from the least significant bit. Which one of the following… Read More
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let Ai represent the logic level on the line… Read More
Consider line number 3 of the following C- program. int main ( ) {                   /* Line 1 */   int I, N;                      /* Line 2 */… Read More

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