Consider the following four schedules due to three transactions (indicated by the subscript) using read and write on a data item x, denoted by r(x)… Read More
Consider a selective repeat sliding window protocol that uses a frame size of 1 KB to send data on a 1.5 Mbps link with a… Read More
Let the size of congestion window of a TCP connection be 32 KB when a timeout occurs. The round trip time of the connection is… Read More
Consider a token ring network with a length of 2 km having 10 stations including a monitoring station. The propagation speed of the signal is… Read More
Identify the correct order in which the following actions take place in an interaction between a web browser and a web server. The web browser… Read More
Which of the following are used to generate a message digest by the network security protocols? (P) RSA (Q) SHA-1 (R) DES (S) MD5 (A)… Read More
Consider the following three statements about link state and distance vector routing protocols, for a large network with 500 network nodes and 4000 links. [S1]… Read More
Given the following statements: S1: A foreign key declaration can always be replaced by an equivalent check assertion in SQL. S2: Given the table R(a,b,c)… Read More
Consider the relation scheme R = {E, F, G, H, I, J, K, L, M, M} and the set of functional dependencies {{E, F} ->… Read More
Which one of the following is FALSE? (A) User level threads are not scheduled by the kernel. (B) When a user level thread is blocked,… Read More
Suppose a disk has 201 cylinders, numbered from 0 to 200. At some time the disk arm is at cylinder 100, and there is a… Read More
Match the following: 1) Waterfall model a) Specifications can be developed incrementally 2) Evolutionary model b) Requirements compromises are inevitable 3) Component-based c) Explicit recognition… Read More
Which one of the following is FALSE? (A) A basic block is a sequence of instructions where control enters the sequence at the beginning and… Read More
A machine has a 32-bit architecture, with 1-word long instructions. It has 64 registers, each of which is 32 bits long. It needs to support… Read More
(A) {q0, q1, q2} (B) {q0, q1} (C) {q0, q1, q2, q3} (D) {q3} Answer: (A) Explanation: So, q0, q1 and q2 are reachable… Read More