Multistage Switching Network – Interconnection structure in Multiprocessor System
In this article, we are going to cover the interconnection structure that is commonly used but in this section, we will more focus on Multistage Switching networks in detail. Let’s discuss it one by one as follows.
The processors must be able to share a set of main memory modules & I/O devices in a multiprocessor system. This sharing capability can be provided through interconnection structures. The interconnection structure that is commonly used can be given as follows.
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- Time shared / Common Bus (Discussed earlier)
- Cross-bar Switch
- Multiport Memory
- Multistage Switching Network
- Hypercube System
Let’s discuss it one by one as follows.
- Time-shared / Common Bus :
In a multiprocessor system, the time-shared bus interconnection provides a common communication path connecting all the functional units.
- Cross-bar Switch :
A point is reached at which there is a separate path available for each memory module if the number of buses in the common bus system is increased. Crossbar Switch (for multiprocessors) provides a separate path for each module.
- Multi-port Memory :
In the Multi-port Memory system, the control, switching & priority arbitration logic are distributed throughout the crossbar switch matrix which is distributed at the interfaces to the memory modules.
- Hypercube Interconnection :
This is a binary n-cube architecture. Here we can connect 2n processors and each of the processors here forms a node of the cube. A node can be a memory module, I/O interface also, not necessarily a processor. The processor at a node has a communication path that is direct goes to n other nodes (total 2n nodes). There is a total of 2n distinct n-bit binary addresses.
- Multistage Switching Network :
- The 2×2 crossbar switch is used in the multistage network. It has 2 inputs (A & B) and 2 outputs (0 & 1). To establish the connection between the input & output terminals, the control inputs CA & CB are associated.
- The input is connected to 0 output if the control input is 0 & the input is connected to 1 output if the control input is 1. This switch can arbitrate between conflicting requests. Only 1 will be connected if both A & B require the same output terminal, the other will be blocked/ rejected.
- We can construct a multistage network using 2×2 switches, in order to control the communication between a number of sources & destinations. Creating a binary tree of cross-bar switches accomplishes the connections to connect the input to one of the 8 possible destinations.
- In the above diagram, PA & PB are 2 processors, and they are connected to 8 memory modules in a binary way from 000(0) to 111(7) through switches. Three levels are there from a source to a destination. To choose output in a level, one bit is assigned to each of the 3 levels. There are 3 bits in the destination number: 1st bit determines the output of the switch in 1st level, 2nd bit in 2nd level & 3rd bit in the 3rd level.
- Example: If the source is: PB & the destination is memory module 011 (as in the figure): A path is formed from PB to 0 output in 1st level, output 1 in 2nd level & output 1 in 3rd level.
- Usually, the processor acts as the source and the memory unit acts as a destination in a tightly coupled system. The destination is a memory module. But, processing units act as both, the source and the destination in a loosely coupled system.
- Many patterns can be made using 2×2 switches such as Omega networks, Butterfly Network, etc.
Interconnection structure can decide the overall system’s performance in a multi-processor environment. To overcome the disadvantage of the common bus system, i.e., availability of only 1 path & reducing the complexity (crossbar have the complexity of O(n2))of other interconnection structure, Multi-Stage Switching network came. They used smaller switches, i.e., 2×2 switches to reduce the complexity. To set the switches, routing algorithms can be used. Its complexity and cost are less than the cross-bar interconnection network.