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Micro Instruction Sequencing

  • Last Updated : 31 May, 2021

Need for designing the micro-instruction sequencing technique : 
The first purpose is to minimize the size of control memory because control memory is present inside the processor.
The second purpose is to execute the micro-instructions as fast as possible. Which means the address of the next micro-instruction can be calculated as fast as possible.

The factors which are responsible for reducing the size of control memory are –

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  • Degree of parallelism i.e. how many microoperations which can be performed simultaneously.
  • Representation/encoding of control information.
  • The way of specifying the address of next microinstruction.

The number of microoperations executed in the processor depends upon the processor architecture, and encoding of instructions makes it short. But the major concern is to calculate the address of the next micro-instruction. 



The address of the next micro-instruction can be –

  • The address of the next micro-instruction in the sequence i.e. one after the other.
  • Branch address(which can be conditional or unconditional).
  • Calculated on the basis of the opcode of the instruction.

 The address of the first micro-instruction can be calculated once from the opcode of the instruction which is present in the instruction register, then that address is loaded into CMAR (Control Memory Address Register). CMAR passes the address to the decoder. The decoder identifies the corresponding micro-instructions from the Control Memory. 
A micro-instruction has two fields: a control field and an address field. 

  • Control field –  
    Determines which control signals are to be generated.
  • Address field – 
    Determines the address of the next micro-instruction.
  • This address is further loaded into CMAR to fetch the next micro-instruction.

As we know, usually micro-instructions are not executed sequentially for a long time . Let’s say after 4 or 5 micro-instructions the branch can usually occur. Therefore, our main motive is to make the branching algorithm better so that the address of the next micro-instruction can be calculated efficiently. 
Therefore, micro-instruction sequencing is the method of determining the flow of the microprogram.

So there are techniques which are based on the number of addresses utilised for sequencing –

  1. Two address fields in each microinstruction (Dual address field).
  2. Single address field(Single address field).
  3. Variable format microinstructions

1. Dual address field –

Dual address field

.

  • In this approach, micro-instructions are not executed in a sequential manner.
  • The instruction register (IR) gives the address of the first micro-instruction.
  • Thereafter, each micro-instruction gives the address of the next micro-instruction.
  • If it is a conditional micro-instruction, it will contain two address fields.
  • One for the condition to be true and the other for false. Hence, it is called dual address field.
  • The multiplexer will decide the address that will be loaded into the control memory address register (CMAR) based on the status flags.

Here, lots of control memory is wasted because at least one of the address fields is not required in many(i.e. for sequential or unconditional) micro-instructions.

2. Single address field –
With some modifications and the added logic, the number of addresses is reduced to one. Here, a new register called microprogram counter is used. In this case, the next microinstruction address can be the address of the next sequential address or it can be the address generated using op-code or it can be the address stored in the address field of the microinstruction. 

Single address field.

  • In this approach, micro-instructions are executed in a sequential manner.
  • The instruction register (IR) gives the address of the first micro-instruction into CMAR.
  • Thereafter, the address is simply incremented.
  • Hence, every micro-instruction need not carry the address of the next one.
  • This is true so long as the micro-program is executed in a sequential manner.
  • For an unconditional branch, the micro-instructions include the branch address. This address will be loaded into CMAR.
  • For a conditional branch, the micro-instruction contains the branch address for true condition. If the condition is false, the current address in CMAR will be simply incremented.
  • This means even in the worst case, the micro-instruction will carry only one address.
  • Hence, it is called single address field.
  • The multiplexer will decide the address that will be loaded into the control memory address register (CMAR) based on the status flags.

This method is commonly used. But the space provided in each micro-instruction in a single address field is not quite useful if the instructions are executed sequentially.  

3. Variable address format –

  • In this technique two formats are used. In such a technique, one bit is needed in the microinstruction to differentiate between control microinstruction or a branching microinstruction. The first format provides the control microinstruction(i.e. the bits are used to generate control signals) , while the second format provides the branch logic and address(there can be conditional or unconditional branch).
  • In the first format, the microinstruction contains control signals, then the next microinstruction address is calculated either by using the op-code of the instruction register or it is the address of the next microinstruction in sequence. In this approach, an extra cycle is needed for branch microinstruction.

Variable instruction format

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