# Logic Synthesis in Digital Electronics

The process of resolving into component parts or analyzing, interpreting, translating, optimizing (rearranging or rewriting to improve efficiency), and mapping RTL (Register Transfer Level) code into a particular and indicated cell library.

Programmed production of logic components in a specific digital circuit which may involve various kinds of complex combinations of logic gates and transistors. If a digital design is at the **Register-Transfer-Level**** **logic synthesis then convert it into **Gate-Level **implementation. It plays an important role in removing the gap and linking high-level synthesis and physical design mechanization.

### History of Logic Synthesis:

In the early stages of the development of logic Synthesis, engineers used to design and optimize electronic circuits using pen and paper (the traditional method) and would do the iterations of the truth table with the help of Karnaugh maps. After technological developments, it was done through Computer systems to do logic minimization.

#### Drawbacks in the existing system:

- Code and logic designs had to be manually written on paper.
- There was a limitation on the number of variables that could be used in the logic design.
- Could only design very small and simple designs that could not perform complex problems.

### Need for Logic Synthesis:

By implementing logic synthesis we can use a greater number of electronic devices. By Moore’s Law, the number of electronic components such as logic gates and transistors keeps on doubling within a span of 18 months which further leads to more compact design requirements and a very high density of ICs.

For greater performance, we have to manufacture more compact designs and put gates and other components as close as they can be so as to reduce the distance between them. This will ultimately lead to faster conduction, reduce delays, and will cause higher frequency operation.

The development of Logic Design led to a reduction in the ASIC design cycle.

### ASIC Design:

ASIC design is a procedure for reduction in cost and size of an electronic circuit through contraction and integration of various kinds of electronic chips into one sole element, this is called – Application Specific Integrated Circuit.

ASIC Design Cycle includes steps such as:

- Design conceptualization
- Chip optimization
- Logical and physical implementation
- Design validation and verification.

**Chip specification:**Microarchitecture, specifications, functionalities, and features are defined.**Functional verification:**Runs simulation at the design level and checks the functionality of the circuit.**RTL block Synthesis:**Translate RTL code into gate-level netlist by logical synthesis under the constraints.**Partitioning of chip:**The chip is partitioned into numerous functional blocks all linked to each other in a hierarchical order in a way such that the chip is energy efficient, occupies a small area, and is not expensive.**Floor planning:**it is the blueprint of the physical implementation of the chip.**Clock tree synthesis:**Setting up the clock tree and consulting the predefined timing, power requirements, and area.**Final verification:**The final step of physical verification is just to check if there are any errors in the circuit.

ASIC Design Cycle

### Prerequisite for Synthesis of the logic gate :

- We should know to want we want as output
- Identify the specifications of the circuit
- We should know its efficiency, frequency, power used, time is taken, size, and feasibility of manufacturing.
- What kind of technology has to be implemented for the synthesis.
- Put the design in the form of Verilog code which is called RTL.

### RTL: Register Transfer Level:

It is a Hardware Description Language (HDL) for the synthesis of digital circuits. The circuits can be defined as a collection of registers, Boolean equations, and control logic statements

For e.g. if- then -else statements can be used to perform controlled functions which can be combined together to make a complex operation. It is used to create high-level representations of circuits.

### Logic Design:

Computers do not understand any language except binary, they work on a 2-valued logic system of 1 and 0. Computers are required to execute several arithmetic operations which they carry out through logic gates.

Logic gates are constructed of integrated circuits which have input signals and output signals and work on binary number systems. Different kinds of combinations of logic gates are used to execute different kinds of programs.

For e.g. Addition, Subtraction, multiplication(repeated addition), inverting, etc.

There are seven types of logic gates:

- AND GATE
- OR GATE
- NOT GATE
- NAND GATE
- NOR GATE
- XOR GATE
- XNOR GATE

By connecting different sequences of logic gates together in different manners, new devices can be constructed that can perform basic or even complex arithmetic functions.

### Goals of logic synthesis:

- Minimize the size of the logic gate cell count and cell size
- Minimize power while switching between gates
- Maximize performance in terms of clock performance of synchronous systems and throughput for asynchronous
- Quickly produce accurate Functional models
- Produce predictable and accurate results timing area and power consumption calculations should correspond with the actual values measured on the physical device once manufactured.

### Logic Synthesis Flow:

**Syntax Analysis:**Takes input of HDL files and checks for syntax errors.**Library Definition:**Provides and allocates standard cells and IP libraries.**Elaboration and Binding:**Translates RTL into the Boolean structure. Binds all cells and makes libraries available.**Constraint Definition:**For building a customized and specific chip, we need to define constraints according to which the chip will function. For e.g. clock frequency, power efficiency, etc.**Pre-mapping Optimization:**It performs mapping to generic cells in the library.**Technology Mapping:**Performs mapping of the generic libraries to technology libraries.**Post-mapping Optimization:**Changes gate designs to meet constraints.**Report and export:**Give out the end results with reports on timings and export.

### Implementation of Logic Synthesis:

**1. OR Multiplexer:**

/*Register transfer Language*/ module OR (i, j, s0, s1, k); input [3:0] i; input [3:0] j; input s0, s1; output [3:0] k; reg k; always @ (i or j or s0 or s1) if (!s0 && s1 || s0) k=i; else k=j; endmodule

**2. Full Adder:**

/*Register Transfer Language*/ module fulladder (input [3:0] a, input [3:0] b, input c_in, output c_out, output [3:0] sum); assign {c_out, sum} = a+b+c_in; endmodule

## Please

Loginto comment...