Skip to content
Related Articles

Related Articles

Handler’s Classification in Computer Architecture

Improve Article
Save Article
  • Difficulty Level : Easy
  • Last Updated : 28 Apr, 2022
Improve Article
Save Article

In 1977, Wolfgang Handler presented a computer architectural classification scheme for determining the degree of parallelism and pipelining built into the computer system hardware. Parallel systems are complicated to the program as compared to the single processor system because parallel system architecture varies according to the multiple CPUs and they must be coordinated or synchronized.

In Handler’s classification pipeline processing systems are  divided into three subsystems:

  1. Processor Control Unit (PCU): Each PCU corresponds to one processor or one CPU.
  2. Arithmetic Logic Unit (ALU): ALU is equivalent to the processing element (PE).
  3. Bit Level Circuit (BLC): BLC corresponds to the combinational logic circuit required for 1-bit operations in ALU.

ALU is a small unit that has fewer features than the processor and it works under the instructions of the processor. ALU is designed for performing arithmetic and logical calculations as per its name. A system comprises multiple ALUs to run parallel and increase the performance of the system. BLC(Bit-level circuit) is required to perform single or bit operations in ALU.

Handler’s classification uses three pairs of integers containing 6 independent entities that describe the computer system:

Computer = <K * K',D*D',W*W'>

where K = number of processors (PCUs) within the computer

  • K’ = number of PCUs that can be pipelined
  • D = number of ALUs (PEs) under the control of PCU
  • D‘ = number of PEs that can be pipelined
  • W = word length of a PE
  • W’ = number of pipeline stages in all PEs

Example 1: Let us consider an example of Texas Instruments’ Advanced Scientific Computer (TI ASC), which has one controller that controls 4 arithmetic pipelines, each having a 64-bit word length and 8 pipeline stages.

From this data, we get K = 1, K’ = 1, D = 4, D’ = 1, W = 64, W’ = 8 . So, we can represent TI ASC  according to Handler’s classification as follows :

 TI ASC = <1*1,4*1,64*8> or <1,4,64*8>

Let us now look at one more exercise on Handler’s classification. 

Example 2: CDC 6600 has only a single CPU with an ALU, that has 10 specialized hardware functions each of 60-bit word length and up to 10 of these functions can be linked into a longer pipeline. It also has 10 peripheral I/O processors which operate in parallel with the CPU and with each other also. Each of the I/O processors has 1 ALU with 12 bits of word length.

Here, we have two parts to consider, i.e. Central processor(CP) and I/O Processor(IP). So, the representation is given by,

CDC 6600 = <CP>*<IP>

From the given information it can be observed that for the Central processor, K = 1, K’ = 1, D = 1, D’ = 10, W = 60, W’ = 1 and for the I/O processor, K = 10, K’ = 1, D = 1, D’ = 1, W = 12, W’ = 1

Hence, the expression becomes,

CDC 6600 = <1*1,1*10,60*1> * <10*1,1*1,12*1> or <1,10,60>*<10,1,12>

My Personal Notes arrow_drop_up
Related Articles

Start Your Coding Journey Now!