# GATE | GATE-CS-2005 | Question 62

• Last Updated : 29 Sep, 2021

Consider the following circuit involving a positive edge triggered D FF.

Consider the following timing diagram. Let Ai represent the logic level on the line A in the i-th clock period.

Let A’ represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 is
(A) A0 Al A1′ A3 A4
(B) A0 Al A2′ A3 A4
(C) Al A2 A2′ A3 A4
(D) Al A2′ A3 A4 A5′

Explanation: The Flip Flop used here is a Positive edge triggered D Flip Flop, which means that only at the “rising edge of the clock” flip flop will capture the input provided at D and accordingly give the output at Q. And at other times of the clock the output doesn’t change. The output of D flip flop is same as input, i.e. Y=Q=D ( at the rising edge ).

Now, in the question above, 5 clock periods are given, and we have to find the output Q or Y in those clock periods.

First, let’s derive the boolean expression for the Logic gate.

which is :
D = AX + X’ Q’

Now,

In the 1st clock period, (i.e. when t = 0 to 1 )

here the clock has rising edge at t= 0, hence at this moment only, D flip flop will change its state.

In the 1st clock,  X = 1, So,  D = A. Now A logic line may have different levels at different clock periods, i.e. may be high or low, therefore we have to answer with respect to the ith clock period where Ai is the logic level ( high or low ) of logic line A in the ith clock.

So in the 1st clock period, A logic value should be A1 ( i.e. value of A in 1st clock period), but due to the delay provided by the Logic Gates ( Propagation Delay) the value of A used by Flip Flop is previous value of A only, i.e.it will capture the value of D resulted by using the logic line A in the 0th clock period, which is A0. Same happens with the value of X, i.e. instead of Xi, previous value of X  is used in the in the ith clock period, which is Xi-1.

Now, In the 1st clock period value of X is same as in the 0th clock, i.e. logic 1. So, X = 1 ,and A = A0, therefore, D = A0, and hence Q = Y = A0

Similarly we have to do for other clock periods, i.e. instead of taking Ai and Xi,  Ai-1 and Xi-1 need to be taken for getting the output in the ith clock period.

In the 2nd clock period, (i.e. when t = 1 to 2 )

X = 1 ( value in the previous clock), So, D = A1 ( value of A in the previous clock)  , therefore Q = Y = A1

In the 3rd clock period, (i.e. when t = 2 to 3 )

X = 0 ( value in the previous clock,see the timing diagram), So, D = Q’ = A1′ , therefore Q = Y = A1′   ( because of the feedback line )

In the 4th clock period, (i.e. when t = 3 to 4 )

X = 1 ( value in the previous clock,  ), So, D = A3 , therefore Q =  Y = A3

In the 5th clock period, (i.e. when t = 4 to 5 )

X = 1 ( value in the previous clock ), so, D = A4 , therefore Q = Y = A4

Hence the output sequence is : A0 A1 A1′ A3 A4.

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