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GATE | GATE-CS-2004 | Question 90

  • Last Updated : 19 Sep, 2019

Consider the partial implementation of a 2-bitt counter using T flip-flops following the sequence 0-2-3-1-0, as shown below
GATECS20014Q61


To complete the circuit, the input X should be
(A) Q2′
(B) Q2 + Q1
(C) (Q1 ⊕ Q2)’
(D) Q1 ⊕ Q2


Answer: (D)

Explanation: From circuit we see T1=XQ1’+X’Q1—-(1)

AND T2=(Q2+Q1)’—-(2)

AND DESIRED OUTPUT IS 00->10->11->01->00

SO X SHOULD BE Q1Q2’+Q1’Q2 SATISFYING 1 AND 2.

SO ANS IS (D) PART.

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