GATE | GATE-CS-2003 | Question 10
For a pipelined CPU with a single ALU, consider the following situations
1. The j + 1-st instruction uses the result of the j-th instruction as an operand 2. The execution of a conditional jump instruction 3. The j-th and j + 1-st instructions require the ALU at the same time
Which of the above can cause a hazard ?
(A) 1 and 2 only
(B) 2 and 3 only
(C) 3 only
(D) All of above
Explanation: Case 1: Is of data dependency .this can’t be safe with single ALU so read after write.
Case 2:Conditional jumps are always hazardous they create conditional dependency in pipeline.
Case 3:This is write after read problem or concurrency dependency so hazardous
All the three are hazardous
So (D) is correct option.
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