Open in App
Not now

# Full Adder in Digital Logic

• Difficulty Level : Easy
• Last Updated : 09 Jun, 2022

Logical Expression for SUM: = Aâ€™ Bâ€™ C-IN + Aâ€™ B C-INâ€™ + A Bâ€™ C-INâ€™ + A B C-IN = C-IN (Aâ€™ Bâ€™ + A B) + C-INâ€™ (Aâ€™ B + A Bâ€™) = C-IN XOR (A XOR B) = (1,2,4,7)

Logical Expression for C-OUT: = Aâ€™ B C-IN + A Bâ€™ C-IN + A B C-INâ€™ + A B C-IN = A B + B C-IN + A C-IN = (3,5,6,7)

Another form in which C-OUT can be implemented: = A B + A C-IN + B C-IN (A + Aâ€™) = A B C-IN + A B + A C-IN + Aâ€™ B C-IN = A B (1 +C-IN) + A C-IN + Aâ€™ B C-IN = A B + A C-IN + Aâ€™ B C-IN = A B + A C-IN (B + Bâ€™) + Aâ€™ B C-IN = A B C-IN + A B + A Bâ€™ C-IN + Aâ€™ B C-IN = A B (C-IN + 1) + A Bâ€™ C-IN + Aâ€™ B C-IN = A B + A Bâ€™ C-IN + Aâ€™ B C-IN = AB + C-IN (Aâ€™ B + A Bâ€™)

Therefore COUT = AB + C-IN (A EX â€“ OR B)

2 Half Adders and an OR gate is required to implement a Full Adder.

With this logic circuit, two bits can be added together, taking a carry from the next lower order of magnitude, and sending a carry to the next higher order of magnitude.

### Implementation of Full Adder using NAND gates: Implementation of Full Adder using NOR gates:

Total 9 NOR gates are required to implement a Full Adder. In the logic expression above, one would recognize the logic expressions of a 1-bit half-adder. A 1-bit full adder can be accomplished by cascading two 1-bit half adders.

My Personal Notes arrow_drop_up
Related Articles