External Memory Interfacing in 8051 Microcontroller
For minimal memory applications, the 8051 has internal data and code memory. In such a position. For certain applications, this memory capacity will not be adequate. To expand the memory space of the 8051 micro-controller, we must bind external ROM/EPROM and RAM. We also understand that ROM serves as program memory and RAM serves as data memory. Let’s take a look at how the 8051 accesses these memories.
External Program Memory :
- The program fetches to addresses 0000H through OFFFH are directed to the internal ROM in the 8051 when the EA pin is attached to Vec, and program fetches to addresses 1000H through FFFFH are directed to the external ROM/EPROM. When the EA pin is grounded, all addresses fetched by the program (0000H to FFFFH) are led to it.
- ROM/EPROM that is external to the device. As seen in Fig. 1, the PSEN signal is used to trigger output e external ROM/EPROM.
- Port 0 is used as a multiplexed address/bus, as seen in Fig2. In the initial T-cycle, it provides a lower order 8-bit address, and later it is used as a data bus. The external latch and the ALE signal provided by the 8051 are used to latch the 8-bit address.
- Remote ROM/EPROM(Read Only Memory/Electronic Programmable ROM/Electronic Programmable ROM/Electronic Program The PSEN signal is used to activate output e external ROM/EPROM, as seen in Fig. 1.
- As seen in Fig2, port 0 is used as a multiplexed address/bus. It supplies a lower-order 8-bit address in the first T-cycle and later serves as a data bus. The 8-bit address is latched using the external latch and the ALE signal given by the 8051.
- 1External Interrupt 0 is 0003H, Timer 0 is 000BH, External Interrupt 1 is 0013H, Timer 1 is 001BH, and so on. If an interrupt is to be used, the operation routine for it must be in the same place as the interrupt. If the interrupt isn’t used, the service location may be used as general-purpose program memory.
Instructions to Access External ROM / Program Memory :
This table is explaining the instructions to access external ROM/program memory.
|MOVC A, @ A+DPTR||Copy the contents of the external ROM address formed by adding A and the DPTR, to A|
|MOVC A, @ A + PC||This operation will do copy This operation contents of the external ROM address formed by adding A and the PC, to A.|
External Memory Interfacing :
- Up to 64 k-bytes of additional data memory can be addressed by the 8051. The external data memory is accessed using the “MOVX” instruction.
- The 8051’s internal data memory is split into three sections: Lower 128 bytes, Upper 128 bytes, and SFRs. While they are physically distinct bodies, the upper addresses and SFRs share the same block of address space, 80H by FFH.
- The upper address space is only accessible via indirect addressing, and SFRs are only accessible via direct addressing, as seen in Higher address space, on the other hand, can be reached using either direct or indirect addressing.
- Fig. 7 a and b show the timing waveform for external data memory read and write cycles, respectively.
Instructions to Access External Data Memory :
The Table explains the instruction to access external data memory.
|MOVX A, @Rp||In this operation, it will copy the contents of the external address in Rp to A.|
|MOVX A. @DPTR||Copy the contents of the external address in DPTR to A.|
|MOVX @Rp. A||Copy data from A to the external address in Rp|
|MOVX DPTR, A||Copy data from A to the external address in DPTR.|
Important Points to Remember in Accessing External Memory :
- In the Case of accessing external memory, All external data moves with external RAM or ROM involve the A register.
- While accessing external memory, R can address 256 bytes and DPTR can address 64 k-bytes
- MOV X instruction is used to access external RAM or 1/O addresses.
It must be noted that while the Program counter(PC) will be used then to access external ROM, it will be incremented by 1 (to point to the next instruction) before it is added to A to form the physical address of external ROM.
Memory Address Decoding :
We know that read/write memories consist of an array of registers, in which each register has a unique address: The size of the memory is NX Mas shown in Fig. 11.2.1 (a) where N is the number of registers and M is the word length, in a number of bits.
If memory is having 12 address lines and 8 data lines, then number of registers/memory locations = 2^N= Word length = Mbit = 8-bit.
- If the memory has 8192 memory locations, then it has :3 address lines The Table 11.2.1 summarizes the memory capacity and address lines required for memory interfacing
|Memory Capacity||Address Line Required|
|1 K = 1024 memory locations||10|
|2 K = 2048 memory locations||11|
|4 K = 4096 memory locations||12|
|8K= 8192 memory locations||13|
|16 K = 16384 memory locations||14|
|32 K = 32768 memory locations||15|
|64 K = 65536 memory locations||16|
- The memory chip has 11 address lines A10-A0, one chip pick (CS), and two control lines, as seen in the table. To allow the output buffer, press RD, and to enable the input buffer, press WR.
- The address lines are decoded using the internal decoder: (b) displays the logic diagram of a 4096 (4 K) register EPROM (Erasable Programmable Read-Only Memory).
- It has a total of 12 address blocks. One chip pick (CS) and one read control signal (A11-A0). EPROM does not need the (WR) signal since it is a read-only memory.
- Memory and 1/0 modules are used in the microprocessor/microcontroller framework. Since the data, address, and control buses are shared by all devices, the microprocessor can only communicate (read/write) with one device at a time.
- It is essential to decoding the address from the microprocessor/microcontroller in order to connect with memory or I/O devices. The strategies for decoding addresses are described in the following section.
- The memory interfacing requires to following components as follows.
- Select the chip.
- Identify the register.
- Enable the appropriate buffer.
Address Decoding Techniques :
- Absolute decoding/Full decoding
- Linear decoding/Partial decoding
Absolute decoding –
- In this technique, all the higher address lines are decoded to select the memory chip, and the memory chip is chosen only for the logic levels defined in these high-order address lines and no other logic levels will select the chip.
- The memory interface with utter encoding is seen in Figure 11.22. In massive memory structures, this addressing strategy is commonly used.
Memory Map –
|Starting address of EPROM||0||0||0||0||0||0||0||0||0||0||0||0||0||0||0||0||0000H|
|End address of EPROM||0||0||0||0||0||0||1||1||1||1||1||1||1||1||1||1||03FFH|
|Starting address of RAM||0||0||1||0||0||0||0||0||0||0||0||0||0||0||0||0||2000H|
|End address of RAM||0||0||1||0||0||0||1||1||1||1||1||1||1||1||1||1||23FFH|
Linear decoding –
- Individual high-order address lines can be used to pick memory chips in compact systems, eliminating the need for hardware for decoding logic. Linear decoding is the term for this method.
- The addressing of RAM using the linear encoding technique is seen in Figure 10. Partial decoding is another name for this process.
- It lowers the cost of encoding and circuitry, but it has the disadvantage of requiring multiple addresses (shadow addresses).
- The addressing of RAM using the linear encoding technique is seen in Figure 10. After inversion, A is a line attached to the chip select signal of the EPROM and then to the chip select signal of the RAM. As a result, EPROM is selected when the status of A line is “empty,” and RAM is selected when the status of the A15 line is “one.” Since the other address lines aren’t used to generate chip pick signals, their status isn’t taken into account.
Memory Map –
|Starting address of EPROM||0||x||x||x||x||x||0||0||0||0||0||0||0||0||0||0||0000H|
|End address of EPROM||0||x||x||x||x||x||1||1||1||1||1||1||1||1||1||1||03FFH|
|Starting address of RAM||1||x||x||x||x||x||0||0||0||0||0||0||0||0||0||0||8000H|
|End address of RAM||1||x||x||x||x||x||1||1||1||1||1||1||1||1||1||1||83FFH|