In a k-way set associative cache, the cache is divided into v sets, each of which consists of k lines. The lines of a set are placed in sequence one after another. The lines in set s are sequenced before the lines in set (s+1). The main memory blocks are numbered 0 onwards. The main memory block numbered j must be mapped to any one of the cache lines from.
(j mod v) * k to (j mod v) * k + (k-1)
(j mod v) to (j mod v) + (k-1)
(j mod k) to (j mod k) + (v-1)
(j mod k) * v to (j mod k) * v + (v-1)
Question 1 Explanation:
Number of sets in cache = v. So, main memory block j will be mapped to set (j mod v), which will be any one of the cache lines from (j mod v) * k to (j mod v) * k + (k-1). (Associativity plays no role in mapping- k-way associativity means there are k spaces for a block and hence reduces the chances of replacement.)
A RAM chip has a capacity of 1024 words of 8 bits each (1K × 8). The number of 2 × 4 decoders with enable line needed to construct a 16K × 16 RAM from 1K × 8 RAM is
Question 2 Explanation:
RAM chip size = 1k ×8[1024 words of 8 bits each] RAM to construct =16k ×16 Number of chips required = (16k x 16)/ ( 1k x 8) = (16 x 2) [16 chips vertically with each having 2 chips horizontally] So to select one chip out of 16 vertical chips, we need 4 x 16 decoder. Available decoder is 2 x 4 decoder To be constructed is 4 x 16 decoder Hence 4 + 1 = 5 decoders are required.
A computer has a 256 KByte, 4-way set associative, write back data cache with block size of 32 Bytes. The processor sends 32 bit addresses to the cache controller. Each cache tag directory entry contains, in addition to address tag, 2 valid bits, 1 modified bit and 1 replacement bit. The number of bits in the tag field of an address is
Question 3 Explanation:
A set-associative scheme is a hybrid between a fully associative cache, and direct mapped cache. It's considered a reasonable compromise between the complex hardware needed for fully associative caches (which requires parallel searches of all slots), and the simplistic direct-mapped scheme, which may cause collisions of addresses to the same slot (similar to collisions in a hash table). (source: http://www.cs.umd.edu/class/spring2003/cmsc311/Notes/Memory/set.html). Also see http://csillustrated.berkeley.edu/PDFs/handouts/cache-3-associativity-handout.pdf Number of blocks = Cache-Size/Block-Size = 256 KB / 32 Bytes = 213 Number of Sets = 213 / 4 = 211 Tag + Set offset + Byte offset = 32 Tag + 11 + 5 = 32 Tag = 16
Consider the data given in previous question. The size of the cache tag directory is
Question 4 Explanation:
16 bit address 2 bit valid 1 modified 1 replace Total bits = 20 20 × no. of blocks = 160 K bits.
An 8KB direct-mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following. 1 Valid bit 1 Modified bit As many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store meta-data (tags) for the cache?
A main memory unit with a capacity of 4 megabytes is built using 1M × 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds. The time required to perform one refresh operation on all the cells in the memory unit is:-
Question 6 Explanation:
Number of chips required for 4MB MM = (4 * 2^20 * 8) / (1 * 2^20) = 32 chips In a refresh cycle, a whole row of a memory chip is refreshed at once. This implies the given time of 100 ns for one refresh operation refreshes one row of memory chip. Since there are 1K=2^10 such rows, time for refreshing a whole chip would be: 2^10 * 100 ns. Second question arises, how to arrange these chips as there can be many possible arrangements. There is a logical arrangement provided in the problem statement itself as "1M x 1 bit chip". This indicates that to make a "1M x 32 bits" MM, we need to arrange all 32 chips in a line. It is to be noted that a row in all chips in series can be refreshed in one refresh cycle. This makes the total time to refresh the 4MBytes of memory as same as that of one chip. Hence, time required to refresh MM = 100 * 2^10 ns. So, option (B) is correct.
A computer system has an L1 cache, an L2 cache, and a main memory unit connected as shown below. The block size in L1 cache is 4 words. The block size in L2 cache is 16 words. The memory access times are 2 nanoseconds. 20 nanoseconds and 200 nanoseconds for L1 cache, L2 cache and main memory unit respectively. When there is a miss in L1 cache and a hit in L2 cache, a block is transferred from L2 cache to L1 cache. What is the time taken for this transfer?
Question 7 Explanation:
A block to access in L2 cache requires 20 nanoseconds, and 2 seconds to place in L1-cache. The block size in L1 cache is 4 words, so total time is =time to access L2 + time to place in L1 = 20+2 = 22 ns.
Consider the data from above question. When there is a miss in both L1 cache and L2 cache, first a block is transferred from main memory to L2 cache, and then a block is transferred from L2 cache to L1 cache. What is the total time taken for these transfers?
Question 8 Explanation:
Since the block size of L2 cache is 16 words and the bandwidth of mainmem->L2 cache is 4 words, it requires a transfer of 4 words 4 times and then a transfer of required 4 words from L2 cache to L1 cache. So total time is 4*(200 + 20) + 1*(20 + 2) = 902 nanoseconds. Option (C) is correct.
How many 32K x 1 RAM chips are needed to provide a memory capacity of 256K-bytes?
Question 9 Explanation:
We need 256 Kbytes, i.e., 256 x 1024 x 8 bits. We have RAM chips of capacity 32 Kbits = 32 x 1024 bits. (256 * 1024 * 8)/(32 * 1024) = 64
Consider a 4-way set associative cache (initially empty) with total 16 cache blocks. The main memory consists of 256 blocks and the request for memory blocks is in the following order: 0, 255, 1, 4, 3, 8, 133, 159, 216, 129, 63, 8, 48, 32, 73, 92, 155. Which one of the following memory block will NOT be in cache if LRU replacement policy is used?
Question 10 Explanation:
4 way set associative so 16 block will be divided in 4 sets of 4 blocks each. We apply(Address mod 4) function to decide set.
All * are misses S1 in the first stage ans S2 in the second.
In the second stage 216 is not present in the cache.
So, (D) is correct option.
There are 60 questions to complete.
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